Prime-grade 4 inch silicon wafer after cutting have sharp edges, as well as they chip effortlessly. The wafer periphery is shaped to eliminate sharp, brittle edges; rounded edges reduce the peril for slipping, too. The edge shaping process makes the wafer completely round, the diameter is attuned, as well as orientation flat(s) or else notch is dimensioned or made.
If the wafer is to be thinned after processing, the wafer edge may, as a consequence be sharp as well as thus brittle utilizing the criterion profile; therefore, an asymmetric edge profile can be utilized. Also, wafer bonding may set precise needs for the wafer edge shape; usually, for bonding applications, a blunter profile is suggested in order to accomplish a good bond up to wafer edge.
Silicon wafers have been utilized plentifully in microelectronics as well as MEMS as a platform for fabrication. An interesting difference of the pattern silicon wafer is the SOI substrate. To generate these wafers, two silicon wafers are bonded together, utilizing silicon dioxide of roughly 1–2 μm thickness as a bond layer. One of the silicon wafers is insipid down to a breadth of 10–50 μm. The precise layer breadth will depend on the application.
Diced silicon wafer with a dry oxide coating with a dry oxide coating have been utilized expensively in microelectronics as well as MEMS as a phase for produce. An entrancing collection of the criterion Diced silicon wafer with a dry oxide covering is the SOI substrate. To suggest these wafers, two silicon wafers are reinforced together, utilizing silicon dioxide of around 1–2 μm thickness as a bond layer.
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